Embodiments of the disclosed technology relate to a method and device for testing a thin film transistor (TFT) on an array substrate.
Thin film transistor liquid crystal displays (TFT-LCDs) have become the main kind of flat panel displays in market due to small volume, low power consumption, no radiation, and the like.
A liquid crystal panel of a LCD is generally formed by assembling together an array substrate and a color filter substrate with a liquid crystal layer interposed therebetween. The array substrate typically comprises a base substrate, on which gate lines and data lines intersecting with each other are provided to define a plurality of pixel units arranged in a matrix form. A thin film transistor (TFT) switching element and a pixel electrode are provided in each of the plurality of pixel units. The color filter substrate may comprise a common electrode formed thereon. The application of a voltage to the pixel electrode of a pixel unit is controlled by a gate signal, and the value of the voltage is determined by a source signal. Thus, the characteristics such as output and transfer characteristics of TFTs are very important for a TFT-LCD to work normally.
In design and manufacturing a TFT-LCD, after an array substrate is formed, the TFTs on the array substrate should be tested on the characteristics to obtain the relevant characteristic parameters and data. In this way, the design and the quality for the TFT-LCD can be examined and checked, and as well these characteristic parameters and data can provide supports for determining sources of failures and optimizing array substrate design and printed circuit board (PCB) signal design.
FIG. 1 is a schematic illustration of a TFT device. As shown in FIG. 1, a TFT comprises a gate electrode G, a source electrode S, and a drain electrode D, and on an array substrate, the gate electrode G is connected with a gate line, the source electrode S is connected with a data line, and the drain electrode is connected with a pixel electrode of a pixel unit. When the TFTs on the array substrate are tested on their characteristics, generally a voltage difference is maintained between the source electrode S (data line) and the drain electrode D (pixel electrode) of each TFT, each gate line (gate electrode) on the array substrate is scanned with a multilevel voltage, and the current (Id) between a test signal line and a corresponding pixel electrode and its change are examined. In this method, the voltages applied to the electrodes (terminals) of each TFT are direct current voltages, and the multilevel voltage applied to a gate line is shown in FIG. 2.
When a same signal is applied to one TFT for a long time period, a time stress effect occurs and disadvantageously affects the characteristics of this TFT. In the above conventional method, because direct current signals are applied to the electrodes of a TFT, in which the gate electrode G is scanned with the multilevel voltage as shown in FIG. 2, a time stress effect tends to occur and make the test results inaccurate and deviate from the real situation, and the real status of the TFT cannot be obtained.